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" ILLIADS: A fast timing and reliability simulator for digital MOS circuits, "
Logic-timing Simulation and the Degradation Delay Model - Side 261
af Manuel J. Bellido, Jorge Juan Chico, Manuel Valencia - 2006 - 267 sider
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Architecture Design and Validation Methods

Egon Börger - 2000 - 376 sider
...88-94 106. Rajski, J., Tyszer, J.: Test Responses Compaction in Accumulators with Rotate Carry Adders; IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 12, No. 4, (April 1993), pp. 531-539 107. Gupta, S., Rajski, J., Tyszer, J.: Arithmetic Adaptive Generators...
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面向微系统芯片的建模方法

杨华中 - 2003 - 224 sider
...Trans, on Computer-Aided Design. 12(5): 672~683, May Shih YH, Leblebici Yusef, and Rang Sung-Mo. 1993. ILLIADS: a fast timing and reliability simulator for digital MOS circuits. IEEE Trans, on Computer-Aided Design. 12(9): 1387 ~ 1402, September Shih YH, Kang Sung-Mo. 1992. Analytic...
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Memory, Microprocessor, and ASIC

Wai-Kai Chen - 2003 - 386 sider
...Technical Report ERL-M520, Univ. of California, Berkeley, May 1975. 6. YH Shih, Y. Leblebici, and SM Kang, ILLIADS: A fast timing and reliability simulator for digital MOS circuits, IEEE Trans. Computer-Aided Design, pp. 1387-1402, Sept. 1993. 7. A. Devgan and RA Rohrer, Adaptively controlled...
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