Logic-timing Simulation and the Degradation Delay Model

Forsideomslag
Imperial College Press, 2006 - 267 sider
This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the ?Degradation Delay Model?, developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications.Sample Chapter(s)
 

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Indhold

Fundamentals of Timing Simulation
1
Delay Models Evolution and Trends
23
Degradation and Inertial Effects
47
CMOS Inverter Degradation Delay Model
75
GateLevel DDM
127
Logic Level Simulator Design and Implementation
181
DDM Simulation Results
203
Accurate Measurement of the Switching Activity
227
Copyright

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